AT25QL641 datasheet(23/80 Pages) RENESAS

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DS-AT25QL641-130 Rev. G

Page 23

Sep 14, 2022

AT25QL641 Datasheet

8.3

Write Enable for Volatile Status Register (50h)

This command gives more flexibility to change the system configuration and memory protection schemes

quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register

non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status

Volatile Status Register command does not set the Write Enable Latch (WEL) bit.

When Write Enable for Volatile Status Register command (50h) is executed in QPI Mode, the SUS bit (S15) and

Reserved bits (S13, S12, S11 and S10) of Status Register-2 must be driven high after Write Status Register

command (01h). Once the Read Status Register (05h or 35h) is issued, the read values of the SUS bit (S15) and

Reserved bits (S13, S12, S11 and S10) of the Status Register-2 are ignored.

Figure 6. Write Enable for Volatile Status Register Command for SPI Mode (left) and QPI Mode (right)

8.4

Write Disable (04h)

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register. To enter the

Write Disable command, CS goes low prior to the command 04h into Data Input (SI) pin on the rising edge of

SCK, and then driving CS high. T h e WEL bit is automatically reset upon completion of the every Program,

Erase and Write Status Register commands.

Figure 7. Write Disable Command for SPI Mode (left) and QPI Mode (right)

SCK

234

High-Impedance

Command

50h

Mode 3

Mode 0

Mode 3

Mode 0

Mode 3

Mode 0

Mode 3

Mode 0

HOLD

246

Mode 3

Mode 0

Mode 3

Mode 0

High-Impedance

SCK

Command (04h)

Command

(04h)

Mode 3

Mode 0

Mode 3

Mode 0

HOLD

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