công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

AT25QL641 bảng dữ liệu(PDF) 41 Page - Renesas Technology Corp

tên linh kiện AT25QL641
Giải thích chi tiết về linh kiện  SPI Serial Flash Memory with Dual I/O, Quad I/O, QPI Support
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25QL641 bảng dữ liệu(HTML) 41 Page - Renesas Technology Corp

Back Button AT25QL641 Datasheet HTML 37Page - Renesas Technology Corp AT25QL641 Datasheet HTML 38Page - Renesas Technology Corp AT25QL641 Datasheet HTML 39Page - Renesas Technology Corp AT25QL641 Datasheet HTML 40Page - Renesas Technology Corp AT25QL641 Datasheet HTML 41Page - Renesas Technology Corp AT25QL641 Datasheet HTML 42Page - Renesas Technology Corp AT25QL641 Datasheet HTML 43Page - Renesas Technology Corp AT25QL641 Datasheet HTML 44Page - Renesas Technology Corp AT25QL641 Datasheet HTML 45Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 80 page
background image
DS-AT25QL641-130 Rev. G
Page 41
Sep 14, 2022
© 2022 Renesas Electronics
AT25QL641 Datasheet
8.18 32-kByte Block Erase (52h)
The 32 kB Block Erase command is used for a 32-kByte block erase operation. Prior to the Block Erase
Command, a Write Enable (06h) command must be issued. The command is initiated by driving the CS pin low
and shifting the command code 52h followed b y a 24-bit block address (A23-A0). See Figure 31 and Figure 32
below. The CS pin must go high after the eighth bit of the last byte has been latched in, otherwise the Block Erase
command is not executed. After CS is driven high, the self-timed Block Erase command commences for a time
duration of tBE1 (see Table 26, AC Electrical Characteristics).
While the block erase operation is in progress, the Read Status Register (05h) command may still be used to
read the status of the BUSY bit. The BUSY bit is a 1 during the block erase operation and becomes a 0 when
the cycle is finished and the device is ready to accept other commands again. When the BUSY bit is asserted,
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.
Figure 31. 32 kB Block Erase Command (SPI Mode)
Figure 32. 32 kB Block Erase Command (QPI Mode)
35
246
7
29
31
30
9
8
23
22
2
1
0
01
Mode 3
Mode 0
Mode 3
Mode 0
High-Impedance
SO
SI
SCK
CS
Command (52h)
24-Bit Address
MSB
SCK
CS
1
02
3
4
5
Mode 3
Command
52h
A23-16
A15-8
A7-0
Mode 0
8
12
11
15
14
10
9
13
16
20
18
19
23
22
17
21
IO
IO
IO
IO
0
4
2
3
7
6
1
5
67
Mode 3
Mode 0
MSB



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com