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AT25QL641 bảng dữ liệu(PDF) 42 Page - Renesas Technology Corp

tên linh kiện AT25QL641
Giải thích chi tiết về linh kiện  SPI Serial Flash Memory with Dual I/O, Quad I/O, QPI Support
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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AT25QL641 bảng dữ liệu(HTML) 42 Page - Renesas Technology Corp

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DS-AT25QL641-130 Rev. G
Page 42
Sep 14, 2022
© 2022 Renesas Electronics
AT25QL641 Datasheet
8.19 64-kByte Block Erase (D8h)
The 64 kB Block Erase command is to erase a 64-kByte block of memory. Prior to the Block Erase Command, a
Write Enable (06h) command must be issued. The command is initiated by driving the CS pin low and shifting the
command code D8h followed b y a 24-bit block address (A23-A0). See Figure 33 and Figure 34 below. The CS
pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block Erase command is
not executed. After CS is driven high, the self-timed Block Erase command commences for a time duration of tBE2
(see Table 26, AC Electrical Characteristics).
While the block erase operation is in progress, the Read Status Register (05h) command may still be used to
read the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other commands again. When the BUSY bit is asserted, the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0.
Figure 33. 64-kByte Block Erase Command (SPI Mode)
Figure 34. 64-kByte Block Erase Command (QPI Mode)
35
246
7
29
31
30
9
8
23
22
2
1
0
01
Mode 3
Mode 0
Mode 3
Mode 0
High-Impedance
IO
IO
SCK
CS
Command (D8h)
24-Bit Address
MSB
SCK
CS
1
0
2345
Mode 3
Command
D8h
A23-16
A15-8
A7-0
Mode 0
8
12
11
15
14
10
9
13
16
20
18
19
23
22
17
21
IO
0
4
2
3
7
6
1
5
67
Mode 3
Mode 0
MSB
IO
IO
IO



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