AT25QL641 datasheet(13/80 Pages) RENESAS

13 / 80 page

DS-AT25QL641-130 Rev. G

Page 13

Sep 14, 2022

AT25QL641 Datasheet

Write Protection

To protect inadvertent writes by the possible noise, several means of protection are applied to the Flash memory.

6.1

Write Protect Features

The write protect features are:

▪ While Power-on reset, all operations are disabled and no command is recognized.

▪ An internal time delay of tPUW can protect the data against inadvertent changes while the power supply is

outside the operating specification. This includes the Write Enable, Page Program, Block Erase, Chip Erase,

Write Security Register and the Write Status Register commands.

▪ For data changes, Write Enable command must be issued to set the Write Enable Latch (WEL) bit to 0.

Power-up, Completion of Write Disable, Write Status Register, Page Program, Block Erase and Chip Erase are

subjected to this condition.

▪ Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and BP0) bits may be used to configure

a portion of the memory as read-only (software protection).

▪ The Write Protect (WP) pin can be used to change the Status register (hardware control).

▪ The Deep Power-Down (DPD) mode provides extra protection from unexpected data changes as all

commands are ignored under this status except for the Release from Deep Power-Down command.

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