AT25QL641 datasheet(40/80 Pages) RENESAS

40 / 80 page

DS-AT25QL641-130 Rev. G

Page 40

Sep 14, 2022

AT25QL641 Datasheet

8.17 4-kByte Block Erase (20h)

The Block Erase command is to erase the data of the selected block as being 1. The command is used for 4K-

byte block. Prior to the Block Erase command, the Write Enable (06h) command must be issued. The command

is initiated by driving the CS pin low and shifting the command code 20h followed by a 24-bit block address

(A23-A0) as shown in Figure 29 and Figure 30. The CS pin must go high after the eighth bit of the last byte has

been latched in, otherwise the Block Erase command is not executed. After CS goes high, the self-timed Block

Erase command commences for a time duration of tSE (see Table 26, AC Electrical Characteristics).

While the block erase operation is in progress, the Read Status Register (05h) command may still be accessed

for checking the status of the BUSY bit. The BUSY bit is a 1 during the block erase operation and becomes a 0

when the cycle is finished and the device is ready to accept other commands again. When the BUSY bit is

asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 29. Block Erase Command (SPI Mode)

Figure 30. Block Erase Command (QPI Mode)

SCK

579

829

Command

20h

24-Bit Address

Mode 3

Mode 0

Mode 3

Mode 0

MSB

SCK

345

Mode 3

Command

A23-16

A15-8

A7-0

20h

Mode 0

Mode 3

Mode 0

MSB

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