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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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VR4102 bảng dữ liệu(PDF) 167 Page - NEC |
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VR4102 bảng dữ liệu(HTML) 167 Page - NEC |
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167 / 701 page  CHAPTER 6 EXCEPTION PROCESSING 167 6.3.7 Exception Program Counter (EPC) Register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. The EPC register contains either: — Virtual address of the instruction that was the direct cause of the exception — Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1). The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception- causing instruction contained in the EPC register in the event of another exception. Figure 6-8 shows the format of the EPC register. Figure 6-8. EPC Register Format (a) 32-bit mode 32 0 31 EPC (b) 64-bit mode 64 0 63 EPC EPC: Restart address after exception processing |
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