VR4102 datasheet(43/701 Pages) NEC

43 / 701 page

CHAPTER 1 INTRODUCTION

1.5 VR4100 CPU CORE

Figure 1-2. VR4100 CPU Core Internal Block Diagram

VR4100 CPU core

CPU

CP0

Instruction

Cache

(4K bytes)

Data

Cache

(1K bytes)

Bus

Interface

Clock

Generator

Address/Data(o)

Address/Data(i)

Internal Clock

ID bus

VA bus

Control(o)

Control(i)

TLB

1.5.1 VR4100 CPU Core

(1) CPU bus interface

The CPU bus interface controls data transmission/reception between the VR4100 CPU core and the BCU, which

is one of peripheral units. The VR4100 CPU interface consists of two 32-bit multiplexed address/data buses (one

is for input, and another is for output), clock signals, and control signals such as interrupts.

(2) Clock generator

The following clock inputs are oscillated and supplied to internal units.

x 32.768-kHz clock for RTC unit:

oscillating a 32.768-kHz crystal resonator input via an internal oscillator to supply to the RTC unit.

x 8.432-MHz clock for serial interface and the VR4102’s reference operating clock:

oscillating an 18.432-MHz crystal resonator input via an internal oscillator, and then multiplying it by phase-

locked loop (PLL) to generate a pipeline clock (PClock). The internal bus clock (TClock) is generated from

PClock and supplied to peripheral units.

(3) Instruction cache

The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 4K bytes.

(4) CPU

CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer

data bus, and multiply-and-accumulate operation unit.

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