VR4102 datasheet(73/701 Pages) NEC

73 / 701 page

CHAPTER 2 PIN FUNCTIONS

2.3 PIN STATUS UPON SPECIFIC STATES

2.3.1 Pin Status upon Reset

Table 2-15. Status of Pins upon Reset (1/3)

Signal

When

reset by

RTCRST

When reset by

Deadman’s

Switch or RSTSW

During

Suspend

mode

During Hibernate

mode or when shut

down by HAL timer

During

bus

hold

ADD[25..0]

Note 1

0Hi-Z

DATA[15..0]

Note 1

0Hi-Z

DATA[31..16]/

GPIO[31..16]

Hi-Z

Note 1

Hi-Z

Hi-Z/

Note 1

LCDCS#

Hi-Z

RD#

Hi-Z

WR#

Hi-Z

LCDRDY

ððð

ROMCS[3..0]#

Hi-Z

UUCAS#/MRAS[3]

Note 3

Hi-Z

ULCAS#/MRAS[2]#

Note 3

Hi-Z

MRAS[1..0]#

Note 3

Hi-Z

UCAS#

Note 3

Hi-Z

LCAS#

Note 3

Hi-Z

BUSCLK

Note 2

SHB#

Hi-Z

IOR#

Hi-Z

IOW#

Hi-Z

MEMR#

Hi-Z

MEMW#

Hi-Z

ZWS#

ððð

RSTOUT

Hi-Z

Note 4

IOCS16#

ððð

MEMCS16#

ððð

IOCHRDY

ððð

Notes 1.

The state at the previous Fullspeed mode is retained.

Bus hold from Suspend mode: Outputs the low-level signal

Bus hold from Fullspeed mode or standby mode: Outputs clocks.

Reset by RSTSW# signal: This pin outputs the low-level signal (self refresh)

Reset by Deadman’s Switch: This pin outputs the high-level signal

Normal operations are performed.

Remark

0: outputs low level, 1: outputs high level, Hi-Z: high-impedance

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