VR4102 datasheet(49/701 Pages) NEC

49 / 701 page

CHAPTER 1 INTRODUCTION

1.5.5 Coprocessors (CP0-CP3)

MIPS ISA defines 4 types of coprocessors (CP0 to CP3).

CP1 is reserved to execute a floating-point instruction. CP2 and CP3 are reserved for future use. CP0 is an on-

chip system control coprocessor, which supports the virtual memory system and exception handling. The virtual

memory system is implemented using an on-chip TLB and the CP0 registers in the CPU.

CP0 translates virtual addresses to physical addresses, switches the operating mode, (kernel, supervisor, or user

mode), and management exceptions. It also controls the cache subsystem to analyze a cause and to return from the

error state.

Figure 1-8 shows the definitions of the CP0 register, and Table 1-18 shows simple descriptions of each register.

For the detailed descriptions of the registers related to the virtual system memory, refer to Chapter 5.

For the

detailed descriptions of the registers related to exception handling, refer to Chapter 6.

Figure 1-8. CP0 Registers

for Memory management

** for Exception handling

Reserved

Index*

Random*

EntryLo0*

EntryLo1*

Context**

PageMask*

Wired*

–

BadVAddr**

Count**

EntryHi*

Compare**

Status**

Cause**

EPC**

PRId*

Config*

LLAddr*

WatchLo**

WatchHi**

XContext**

–

PErr**

CacheErr**

TagLo*

TagHi*

ErrorEPC**

–

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