VR4102 datasheet(91/701 Pages) NEC

91 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

Table 3-11. Multiply/Divide Instructions (Extended ISA) (2/2)

Instruction

Format and Description

Multiply and Add 16-

bit Integer

MADD16 rs, rt

The contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by

sign extending to 64 bits). The result is added to the combined value of special registers HI and LO.

The 64-bit result is stored into special registers HI and LO.

Doubleword Multiply

and Add 16-bit Integer

DMADD16 rs, rt

The contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by

sign extending to 64 bits). The result is added to value of special register LO. The 64-bit result is stored

into special register LO.

MFHI and MFLO instructions after a multiply or divide instruction generate interlocks to delay execution of the

next instruction, inhibiting the result from being read until the multiply or divide instruction completes.

Table 3-12 gives the number of processor cycles (PCycles) required to resolve interlock or stall between various

multiply or divide instructions and a subsequent MFHI or MFLO instruction.

Table 3-12. Number of Stall Cycles in Multiply and Divide Instructions

Instruction

Number of instruction cycles

MULT

MULTU

DIV

DIVU

DMULT

DMULTU

DDIV

DDIVU

MADD16

DMADD16

funct

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