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VR4102 bảng dữ liệu(PDF) 47 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
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VR4102 bảng dữ liệu(HTML) 47 Page - NEC

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CHAPTER 1 INTRODUCTION
47
1.5.4 Data Formats and Addressing
The VR4102 uses following four data formats:
Doubleword (64 bits)
Word (32 bits)
Halfword (16 bits)
Byte (8 bits)
For the VR4100 CPU core, byte ordering within all of the larger data formats - halfword, word, doubleword - can
be configured in either big-endian or little-endian order. However, the VR4102 supports the little-endian order
only.
Endianness refers to the location of byte 0 within the multi-byte data structure. Figure 1-5 shows the ordering of
bytes within words and the ordering of words within doubleword structures for the little-endian conventions.
When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is
compatible with iAPXTM and DEC VAXTM conventions. Figure 1-5 shows this configuration.
Figure 1-5. Little-Endian Byte Ordering in Word Data
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12
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15
0
15
16
8
23
24
7
31
8
8
9
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11
4
4
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7
0
0
1
2
3
Lower
address
Higher
address
Word
address
Bit No.
Remarks 1. The lowest byte is the lowest address.
2. The address of word data is specified by the lowest byte’s address.
In this manual, bit 0 is always the least-significant (rightmost) bit; thus, bit designations are always little-endian.
Figure 1-6 shows little-endian byte ordering in doublewords.



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