VR4102 datasheet(92/701 Pages) NEC

92 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

3.2.3 Jump and Branch Instructions

Jump and branch instructions change the control flow of a program. All jump and branch instructions occur with a

delay of one instruction: that is, the instruction immediately following the jump or branch instruction (this is known as

the instruction in the delay slot) always executes while the target instruction is being fetched from memory.

For instructions involving a link (such as JAL and BLTZAL), the return address is saved in register r31.

Table 3-13. Number of Delay Slot Cycles in Jump and Branch Instructions

Instruction

Necessary number of cycles

Branch instruction

Jump instruction

(1) Overview of jump instructions

Subroutine calls in high-level languages are usually implemented with J or JAL instructions, both of which are J-

type instructions. In J-type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4

bits of the current program counter to form a 32-bit or 64-bit absolute address.

Returns, dispatches, and cross-page jumps are usually implemented with the JR or JALR instructions. Both are

R-type instructions that take the 32-bit or 64-bit byte address contained in one of the general-purpose registers.

For more information, refer to Chapter 27.

(2) Overview of branch instructions

A branch instruction has a PC-related signed 16-bit offset.

Tables 3-14 through 3-16 show the lists of Jump, Branch, and Extended ISA instructions, respectively.

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