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VR4102 bảng dữ liệu(PDF) 98 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
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VR4102 bảng dữ liệu(HTML) 98 Page - NEC

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CHAPTER 3 CPU INSTRUCTION SET SUMMARY
98
Table 3-19. System Control Coprocessor (CP0) Instructions (2/2)
Instruction
Format and Description
Read Indexed TLB
Entry
TLBR
The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page
mask register.
Write Indexed TLB
Entry
TLBWI
The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry
indexed by the index register.
Write Random TLB
Entry
TLBWR
The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry
indexed by the random register.
Probe TLB For
Matching Entry
TLBP
The address of the TLB entry that matches with the contents of entryHi register is loaded into the index
register.
Return From
Exception
ERET
The program returns from exception, interrupt, or error trap.
Instruction
Format and Description
STANDBY
STANDBY
The processor’s operating mode is transited from fullspeed mode to standby mode.
SUSPEND
SUSPEND
The processor’s operating mode is transited from fullspeed mode to suspend mode.
HIBERNATE
HIBERNATE
The processor’s operating mode is transited from fullspeed mode to hibernate mode.
Instruction
Format and Description
Cache Operation
Cache op, offset (base)
The 16-bit offset is sign extended to 32 bits and added to the contents of the register case, to form
virtual address. This virtual address is translated to physical address with TLB. For this physical
address, cache operation that is indicated by 5-bit sub-opcode is performed.
COP0
funct
CO
CACHE
offset
base
op
COP0
funct
CO



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