VR4102 datasheet(102/701 Pages) NEC

102 / 701 page

CHAPTER 4 VR4102 PIPELINE

102

4.2 BRANCH DELAY

During a VR4102’s pipeline operation, a one-cycle branch delay occurs when:

x Target address is calculated by a Jump instruction

x Branch condition of branch instruction is met and then logical operation starts for branch-destination

comparison

The instruction address generated at the EX stage in the Jump/Branch instruction are available in the IF stage,

two instructions later.

Figure 4-4 illustrates the branch delay and the location of the branch delay slot.

Figure 4-4. Branch Delay

Branch delay

(Branch delay slot)

Target

Branch

PCycle

4.3 LOAD DELAY

A load instruction that does not allow its result to be used by the instruction immediately following is called a

delayed load instruction. The instruction immediately following this delayed load instruction is referred to as the load

delay slot.

In the VR4102, the instruction immediately following a load instruction can use the contents of the loaded register,

however in such cases hardware interlocks insert additional delay cycles. Consequently, scheduling load delay slots

can be desirable, both for performance and VR-Series processor compatibility.

4.4 PIPELINE OPERATION

The operation of the pipeline is illustrated by the following examples that describe how typical instructions are

executed. The instructions described are: ADD, JALR, BEQ, TLT, LW, and SW. Each instruction is taken through

the pipeline and the operations that occur in each relevant stage are described.

VR4102 bảng dữ liệu(PDF) 102 Page - NEC