VR4102 datasheet(103/701 Pages) NEC

103 / 701 page

CHAPTER 4 VR4102 PIPELINE

103

(1) Add instruction (Add rd, rs, rt)

IF stage

)1 of the IF stage, the eleven least-significant bits of the virtual address are used to access the

instruction cache. In

)2 of the IF stage, the cache index is compared with the page frame number

and the cache data is read out. The virtual PC is incremented by 4 so that the next instruction can

be fetched.

RF stage

During

)2, the 2-port register file is addressed with the rs and rt fields and the register data is valid

at the register file output. At the same time, bypass multiplexers select inputs from either the EX-

or DC-stage output in addition to the register file output, depending on the need for an operand

bypass.

EX stage

The ALU controls are set to do an A + B operation. The operands flow into the ALU inputs, and the

ALU operation is started. The result of the ALU operation is latched into the ALU output latch

during

)1.

DC stage

This stage is a NOP for this instruction. The data from the output of the EX stage (the ALU) is

moved into the output latch of the DC.

WB stage

During

)1, the WB latch feeds the data to the inputs of the register file, which is accessed by the

rd field. The file write strobe is enabled. By the end of

)1, the data is written into the file.

Figure 4-5. Add Instruction Pipeline Activities

IF1

Cycle

Phase

PCycle

PClock

IF2

RF1

RF2

EX1

EX2

DC1

DC2

WB1

WB2

ITLB

IDC

ITC

ICA

IDEC

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