VR4102 datasheet(94/701 Pages) NEC

94 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

There are special symbols used in the instruction formats of Tables 3-15 through 3-19.

REGIMM : Opcode

Sub

: Sub-operation code

: Sub-operation identifier

: BC sub-operation code

: Branch condition identifier

: Operation code

Table 3-15. Branch Instructions

Instruction

Format and Description

Branch On Equal

BEQ rs, rt, offset

If the contents of register rs are equal to that of register rt, the program branches to the target address.

Branch On Not Equal

BNE rs, rt, offset

If the contents of register rs are not equal to that of register rt, the program branches to the target

address.

Branch On Less Than

Or Equal To Zero

BLEZ rs, offset

If the contents of register rs are less than or equal to zero, the program branches to the target address.

Branch On Greater

Than Zero

BGTZ rs, offset

If the contents of register rs are greater than zero, the program branches to the target address.

Instruction

Format and Description

Branch On Less Than

Zero

BLTZ rs, offset

If the contents of register rs are less than zero, the program branches to the target address.

Branch On Greater

Than Or Equal To

Zero

BGEZ rs, offset

If the contents of register rs are greater than or equal to zero, the program branches to the target

address.

Branch On Less Than

Zero And Link

BLTZAL rs, offset

The address of the instruction that follows delay slot is stored to register r31 (link register). If the

contents of register rs are less than zero, the program branches to the target address.

Branch On Greater

Than Or Equal To

Zero And Link

BGEZAL rs, offset

The address of the instruction that follows delay slot is stored to register r31 (link register). If the

contents of register rs are greater than or equal to zero, the program branches to the target address.

Instruction

Format and Description

Branch On

Coprocessor 0 True

BC0T offset

Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the

instruction in the delay slot to calculate out the branch target address. If the conditional signal of the

coprocessor 0 is true, the program branches to the target address with one-instruction delay.

Branch On

Coprocessor 0 False

BC0F offset

Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the

instruction in the delay slot to calculate out the branch target address. If the conditional signal of the

coprocessor 0 is false, the program branches to the target address with one-instruction delay.

offset

REGIMM

offset

sub

COP0

offset

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