VR4102 datasheet(171/701 Pages) NEC

171 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

171

6.3.11 Cache Error Register (27)

The 32-bit read/write Cache Error (CacheErr) register processes parity errors in the on-chip cache. Parity errors

cannot be corrected by on-chip hardware.

The CacheErr register holds cache index and status bits that indicate the cause of the error.

In the VR4102, parity check is performed only for cache memory.

It is not performed for main memory or peripheral units.

Figure 6-12 shows the format of the CacheErr register.

Figure 6-12. CacheErr Register Format

31 30 29 28 27 26 25 24

11 10

ER 0 ED ET 0 EE EB

PIdx

1 1 1 1 1 1 1

ER : Reference type (0

o Instruction, 1 o Data)

ED : Indicates whether an error occurred in the data field (0

o Normal, 1 o Error).

ET : Indicates whether an error occurred in the tag field (0

o Normal, 1 o Error).

EE : This bit is set if an error occurs on the SysAD bus.

EB : This bit is set if a data error occurs subsequent to an instruction error. (The error status is indicated by

the remaining bit positions.)

In this case, the data cache must be flushed upon the completion of

instruction error processing.

PIdx: Cache index

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

6.3.12 ErrorEPC Register (30)

The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the

Program Counter value at which the Cache Error, Cold Reset, Soft Reset, or NMI exception has been serviced.

The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after

servicing an error. This address can be:

— the virtual address of the instruction that caused the error exception

— the virtual address of the immediately preceding branch or jump instruction, when the instruction associated

with the error exception is in a branch delay slot.

The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This

prevents the processor when other exceptions occur from overwriting the address of the instruction in this register

which causes an error exception.

There is no branch delay slot indication for the ErrorEPC register.

Figure 6-13 shows the format of the ErrorEPC register.

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