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VR4102 bảng dữ liệu(PDF) 144 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
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VR4102 bảng dữ liệu(HTML) 144 Page - NEC

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CHAPTER 5 MEMORY MANAGEMENT SYSTEM
144
Figure 5-11. Format of a TLB Entry (2/2)
(c) EntryLo0 and EntryLo1 Registers
27
28
EntryLo1
EntryLo0
EntryLo1
EntryLo0
22
4
0
31
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
27
28
22
4
0
31
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
(a) 32-bit mode
(b) 64-bit mode
27
28
22
36
0
63
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
27
28
22
36
0
63
5
6
3
2
1
0
PFN
C
D
V
G
1
3
1
1
PFN : Page frame number; high-order bits of the physical address.
C
: Specifies the TLB page attribute.
D
: Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is actually a
write-protect bit that software can use to prevent alteration of data.
V
: Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid exception
(TLBL or TLBS) occurs.
G
: Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during TLB
lookup.
0
: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the
cache is used, whether the page attribute is “cached” or “uncached” is selected by algorithm.
Table 5-13 lists the page attributes selected according to the value in the C bits.



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