VR4102 datasheet(141/701 Pages) NEC

141 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

141

5.4 SYSTEM CONTROL COPROCESSOR

The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory

management, address translation, exception handling, and other privileged operations. CP0 contains the registers

shown in Figure 5-9 plus a 32-entry TLB. The sections that follow describe how the processor uses each of the

memory management-related registers.

Remark

Each CP0 register has a unique number that identifies it; this number is referred to as the register

number. See Chapter 1 for details. Also see Chapter 6 for the CP0 functions and the relationships

between exception processing and registers.

Figure 5-9. CP0 Registers and the TLB

Remark

TLB

(Safe entries)

(See Random register for the

TLB Wired boundary.)

127/255

EntryHi

10*

EntryLo0

Index

Context

BadVAddr

Compare

11*

Count

Random

EntryLo1

PageMask

Status

12*

Cause

13*

WatchLo

18*

EPC

14*

Wired

PRId

15*

WatchHi

19*

XContext

20*

ErrorEPC

30*

Cache Error

27*

Parity Error

26*

LLAddr

17*

TagLo

28*

TagHi

29*

Config

16*

*: Register number

Used for memory management

Used for exception processing

Caution

When accessing the CP0 register, some instructions require consideration of the interval time

until the next instruction is executed, because it takes a while from when the contents of the

CP0 register change to when this change is reflected on the CPU operation. This time lag is

called CP0 hazard. For details, see Chapter 28.

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