VR4102 datasheet(147/701 Pages) NEC

147 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

147

5.5.3 EntryHi (10), EntryLO0 (2), EntryLO1 (3), and PageMask (5) Registers

These registers are used in address translation, to rewrite TLB or to find match of TLB entry. When a TLB

exception occurs, the information of the address that causes the exception is loaded into these registers. For the

formats of these registers, see Figure 5-11.

(1) EntryHi Register (10)

The EntryHi register is read/write-accessible.

It is used to access the high-order bits of built-in TLB.

The

EntryHi register holds the high-order bits of a TLB entry for TLB read and write operations. If a TLB Mismatch,

TLB Invalid, or TLB Modified exception occurs, the EntryHi register sets the virtual page number (VPN2) for a

virtual address where an exception occurred and the ASID. See Chapter 6 for details of the TLB exception.

The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the

TLB entry as the ASID of the virtual address during address translation.

The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions.

(2) EntryLo0 (2) and EntryLo1 (3) Registers

The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages

and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible.

They are used to access the low-order bits of the built-in TLB. When a TLB read/write operation is carried out,

the EntryLo0 and EntryLo1 registers hold the contents of the low-order 32 bits of TLB entries at even and odd

addresses, respectively.

(3) PageMask Register (5)

The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison

mask that sets the five types of page sizes for each TLB entry, as shown in Table 5-14. Page sizes must be

from 1 Kbyte to 256 Kbytes.

TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets

of comparison are masked during address translation.

Table 5-14 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB

behaves unexpectedly.

Table 5-14. Mask Values and Page Sizes

Page size

Bit

1 Kbyte

000

0000

4 Kbytes

000

0001

16 Kbytes

000

0111

64 Kbytes

001

1111

256 Kbytes

1111

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