845GL datasheet(135/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

135

Functional Description

DDC (Display Data Channel)

The multiplexed digital display interface uses the MDVI_CLK and MDVI_DATA signals to

interrogate the panel. The GMCH supports the DDC2B protocol to initiate the transfer of EDID

data. The multiplexed digital display interface uses the M_I2C bus to interrogate the external

transmitter.

Optional High Speed (Dual-Channel) Interface

The multiplexed digital display ports can operate in a single 24-bit mode. The 24-bit mode uses the

12-bit DVOC data pins combined with the DVOB data pins to make a 24-bit bus. This doubles the

transfer rate capabilities of the port. In the single port case, horizontal periods have a granularity of

a single pixel clock; in the double case, horizontal periods have a granularity of two pixel clocks. In

both cases, data is transferred on both edges of the differential clock. The GMCH can output the

data in a high-low fashion, with the lower 12 bits of the pixel on one DVO port and the upper

12 bits of data on the other DVO port. In this manner, the GMCH transfers an entire pixel per clock

edge (2 pixels per clock). In addition to this, the GMCH also can transfer dual-channel data in odd-

even format. In this mode, the GMCH transfers all odd pixels on DVOC and all even pixels on

DVOB. In this format, each DVO port sees both the high and low half of the pixel, but only sees

half of the pixels transferred. As in high-low mode, two full pixels are transferred per clock period.

The high-low ordering within each pixel can be modified through DVO control registers.

Intel® DVO Modes

In single channel mode, the order of pixel transmission (high-low vs. low-high) can be adjusted via

the data ordering bit of that DVO port’s control register. As mentioned above, when in dual -

channel mode, the GMCH can transmit data in a high-low or odd-even format. In high-low mode,

software can choose which half goes to which port. A 0 = DVOB Lo/DVOC Hi, and a 1 = DVOB

Hi/ DVOC Lo. In odd/even mode, the odd pixels will always go out to DVOC and even pixels will

always go out to DVOB. Which DVO port is even and which is odd cannot be switched, but the

data order bit can be used to change the active data order within the even and odd pixels. The

GMCH considers the first pixel to be pixel zero and sends it out to DVOB.

4.5.2.2

Synchronous Display

Microsoft Windows* 98 and Windows* 2000 have enabled support for multi-monitor display.

Synchronous mode will display the same information on multiple displays.

Since the GMCH has several display ports available for its single pipe, it can support synchronous

display on two displays, unless one of the displays is a TV. No synchronous display is available

when a TV is in use. The GMCH does not support two synchronous digital displays. The GMCH

cannot drive multiple displays concurrently (different data or timings). In addition, the GMCH

cannot operate in parallel with an external AGP device. The GMCH can, however, work in

conjunction with a PCI graphics adapter.

845GL bảng dữ liệu(PDF) 135 Page - Intel Corporation