STR720RBQ6 datasheet(104/401 Pages) STMICROELECTRONICS

104 / 401 page

STR720 - DRAM CONTROLLER (DRAMC)

104/401

10.4 Register description

The following paragraphs give detailed descriptions and operations of each of the bits in the

DRAMC registers.

Bank 1 Configuration Register (MB1Config)

Address Offset: 00h

Reset value: 0000h

The Bank 1 Configuration Register (MB1Config) is a 16-bit read/write control register used to

configure specific parameters of external region 1 (Bank 1).

The MB1Config control bits are described below.

Bit 15:12 reserved (should be written as zero and ignored on read ).

Bit 11:10 DEVWID[1:0]: Device Width.

This field defines the data width of the external memory device 0.

= 0b00. Byte (8 bit)

= 0b01. Half Word (16 bit)

= 0b10. Word (32 bit)

= 0b11. Reserved.

Bit 9:8

DATALAT[1:0]: Data Latency.

This field defines the number of memory clock cycles between the start of a

memory read access and the first valid data. This parameter is usually indicated in

SDRAM datasheets as CAS latency. The DATALAT value is valid between 0 and 3.

Bit 7:5

SETUPTIME[2:0]: Setup Time.

This field defines the number of memory clock cycles the memory drivers spends

in a wait state before accessing the external memory. This parameter is usually

indicated in SDRAM datasheets as RAS-CAS delay. The SETUPTIME value is

valid between 0 and 7.

Note

SETUPTIME field should be set using the RAS-CAS delay value found on SDRAM

datasheet minus 1. As an example to get a RAS-CAS delay of 2 clock cycles,

SETUPTIME should be configured to 1.

Bit 4:2

IDLETIME[2:0]: Idle Time.

This field defines the minimum time the memory driver must spend in the IDLE

state following memory accesses (the value defines the number of memory clock

cycles). This parameter is usually indicated in SDRAM datasheets as precharge

delay. The IDLETIME value is valid between 0 and 7.

6543210

reserved

DEVWID[1:0]

DATALAT[1:0]

SETUPTIME[2:0]

IDLETIME[2:0]

SDRAMCOL[1:0]

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