STR720RBQ6 datasheet(103/401 Pages) STMICROELECTRONICS

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STR720 - DRAM CONTROLLER (DRAMC)

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10.3.2

APB Interface

The APB Interface contains the DRAM Controller registers and is used only to access these

registers.

The length of time required to properly transfer data from/to external memory is controlled by

an internal Bank Configuration Register which is dedicated to each bank. The data fields of

this register determine the number of memory clock cycles used to access that bank; the

access time also depends on the bus width and the latency of the selected device. A flag bit in

the Memory Configuration Register (one register for all banks) informs the controller if a

particular bank is accessible or not.

To allow the STR720 to directly configure the SDRAM devices, the SDRAM Configuration

Registers are provided. When they are written via the system bus, the DRAM Controller will

drive memory bus output signals with the values from the SDRAM Configuration Registers.

This means that the content of the selected register will be outputted on the memory bus and

the corresponding memory bank chip select will be asserted, for one clock period.

10.3.3

Refresh Timer

A refresh timer is provided to issue refresh commands to SDRAM and EDO devices. Refresh

commands are issued to all banks simultaneously.

When a refresh is requested, the DRAMC waits for any active memory transfer to complete

before activating the refresh.

Any system bus memory transfers started while the refresh is in progress are stalled by the

Controller.

The refresh counter uses an enable signal, synchronous with the rising edge of the system

clock, which is generated by prescaling CLK input signal by 16.

This signal

is used to ensure that the refresh counter operates at the same frequency

regardless of the current system clock configuration depending on PLL and RCCU settings.

If the PWRSAVE bit in the Memory Configuration Register is set to ‘1’ , the refresh logic will

set external memories in the power save self-refresh mode (as long as the bit remain high).

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