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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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STR720RBQ6 bảng dữ liệu(PDF) 48 Page - STMicroelectronics |
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STR720RBQ6 bảng dữ liệu(HTML) 48 Page - STMicroelectronics |
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48 / 401 page  STR720 - MEMORY ORGANIZATION 48/401 6.2 Memory map 6.3 APB Bridges Mapping APB bridges allow the connection between the high performance AHB bus, where ARM720, DMA, memory block and memory interfaces are located, to the peripherals residing on the APB bus. Two separated APB subsystems have been implemented on STR720 device: Asynchronous APB subsystem and Synchronous APB subsystem. They are briefly described in the following sections, along with the related peripheral address mapping. 6.3.1 Asynchronous APB sub-system (A-APB) In order to reduce the power consumption of the overall device, the Asynchronous APB sub-system, in short A-APB, can be clocked at a frequency different from the one used for ARM720T core. A specific asynchronous AHB-APB bridge provides a re-synchronization mechanism in order to enable the master of AHB bus to access the APB peripherals although residing on a different clock domain. 0x0000_0000 EMI EMI 0x4000_0000 4 GBytes Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 ATAPI-IDE Block 6 Block 7 0x6000_0000 0x8000_0000 0xA000_0000 0xC000_0000 0xE000_0000 4 GBytes REMAP Reset Memory Map Remapped Memory Map Non-implemented memory areas 0x2000_0000 SDRAM 0x2000_0FFF 0x6000_3FFF 0x0000_0000 EMI 0x4000_0000 Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 ATAPI-IDE Block 6 Block 7 0x6000_0000 0x8000_0000 0xA000_0000 0xC000_0000 0xE000_0000 0x2000_0000 SDRAM 0x2000_0FFF 0x0000_3FFF 0xF000_0000 A-APB S-APB 0x6000_3FFF 0xF000_0000 A-APB S-APB Reserved Reserved PROG RAM PROG RAM PROG RAM ROM ROM 1 |
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