STR720RBQ6 datasheet(55/401 Pages) STMICROELECTRONICS

55 / 401 page

STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Every clock cycle the IPR (Interrupt Pending Register) is updated and the pending interrupts

are arbitrated to finally activate the IRQ/FIQ request to the CPU.

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Once the interrupt request has been accepted by the CPU, the program execution jumps at

the first instruction of the related interrupt channel software routine (see Section 7.5 for more

details).

The enhanced interrupt controller will automatically:

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Reject/accept an interrupt request according to the channel enable bit (IER - Interrupt

Enable Register).

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Compare all interrupt requests (pending or new) with the current priority interrupt level. If the

priority of the interrupt requests is higher than the current priority, an interrupt IRQ is

asserted.

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The register 0x18 is loaded with the corresponding address vector.

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When an interrupt request is accepted, the previous interrupt priority and channel ID

(content of CIPR and CICR registers) are saved by the EIC in the EIC’s hardware stack.

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The current priority register (CIPR) and the current channel register (CICR) are

automatically updated with the accepted interrupt priority and channel ID.

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When the pending bit in the IPR is cleared, the end of interrupt condition is detected, and the

EIC restores in the CIPR and the CICR the previous interrupt priority and channel ID saved

in the hardware stack.

The EIC allows to mask all the interrupt sources by resetting the enable bits in the ICR (Inter-

rupt Control Register).

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