STR720RBQ6 datasheet(42/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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5.11 Universal Asynchronous Receiver/Transmitter (UART)

STR720 provides 2 Universal Asynchronous Receiver Transmitter peripherals (UART) to

interface to other microcontrollers, microprocessors or external peripherals through serial

communication. Both UARTs support full duplex asynchronous communication with external

peripherals.

Data frames can be either 8-bit long (8 data bits or 7 data bits plus an automatically generated

parity bit) or 9-bit long (9 data bits or 8 data bits plus an automatically generated parity bit or

8 data bits plus a wake up bit, useful for communication in multiprocessor systems). Parity,

framing, and overrun error detection can be automatically added to increase the reliability of

data transfers. An internal 16-bit baud rate generator is available: the clock for both transmit

and receive channels can be obtained dividing the input clock by any divisor value from 1 to

216-1.

In order to reduce the number of interrupt to the ARM7, two internal FIFO’s (16 words of 9 bits

each) can be enabled via software, one for transmitted data and one for received data.

5.12 Buffered Serial Peripheral Interface (BSPI)

STR720 provides two Buffered Serial Peripheral Interfaces (BSPI). The BSPI implements an

industry standard serial synchronous full duplex 4-pin interface, fully compliant with Motorola

SPI protocol. The BSPI can be used to communicate with peripheral devices or it can be used

for inter-processor communications in a multiple-master environment.

The buffered SPI can be configured to operate either in slave or in master mode, even if slave

mode is subject to some limitations since Slave Select lines are shared with external interrupt

1 and 2 lines on P3.9 and P3.10 pads. Two internal FIFO’s (16 words of 16 bits each) are

available, one on the receive channel and one on the transmit channel. The BSPI can be

programmed to operate with words 8 and 16 bit long. The BSPI serial clock frequency can be

programmed dividing the input clock by an even value in the range starting from 6 to 254.

5.13 Controller Area Network Interface (CAN)

Two independent CAN interfaces are implemented on STR720. The Controller Area Network

serial bus is compliant to the CAN Protocol Version 2.0 Part A (messages with 11 bit

identifiers) and B (messages with 29 bit identifiers).

5.14 Universal Serial Bus Interface (USB)

STR720 provides a full speed USB slave interface, compliant with revision 1.1 of the USB

standard, giving a peak transfer rate of 12 Mbits/s. This interface shares its data lines with

pins P2.14 and P2.15, while its clock source is taken from an external clock line, shared with

P2.10, which must be set to 48 MHz (50% duty cycle) when the USB is required. STR720

system features built-in USB transceivers which requires two series resistors of 27

Ω± 5%,

one for each data line, to adapt the output impedance according to USB standard

specifications.

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