STR720RBQ6 datasheet(44/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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of available alternate function I/Os, the number of interrupt events each EFT block can

generate is the same and it is indicated in Section 5.1.1: IRQ Interrupt Vector Table on

page 28.

EFT1 external clock source can be selected by software (in place of system clock) to obtain

time bases independent from the system clock frequency (usually dependent on the selected

system configuration mode) or to count external events.

5.17

Σ−∆ Analog to Digital Converter (ADC)

For analog signal measurement, a 11.5-bit ENOB resolution A/D converter (ADC) with 4

multiplexed input channels. It returns the conversion result on 16 bits with a frequency of up to

950 Hz each channel. It is a second-order quad-channel Sigma-Delta converter specifically

suited for low conversion rate application (512 times oversampling rate). The typical SINAD is

71 dB.

The ADC supports two different conversion modes. In the standard Auto Scan Continuous

mode, the analog levels on each channel are sequentially and repeatedly sampled and

converted. Alternatively, the Single Channel conversion mode, can be used where the analog

level on a specified channel is repeatedly sampled and converted into a digital result without

software intervention.

Each channel has its own result data register where the value obtained from the last

completed conversion is stored. In both modes it is possible to associate a DMA transfer to

the end of conversion interrupt without interrupting the ARM720T for the data transfer.

Only one interrupt source is implemented, called ‘End of conversion’ which is activated each

time a conversion sweep is completed and the result is written on the data result registers.

5.18 General Purpose I/O Ports

The General Purpose IO (GPIO) Ports are programmable by software in several conditions:

Input, Output, Alternate Function, Open Drain, Push-Pull, Bidirectional Weak and high

impedance.

Three General Purpose I/O Ports are available on STR720 system: P2, composed of 16 bits,

P3, composed of 13 bits, and P4, composed of 5 bits only. Although all their registers are

described as 16-bit wide, the actual number of available pins corresponds to what is stated

above and in Chapter 4: PIN DATA on page 14.

During and just after the reset no alternate function is active: in particular each Port bit is

configured in Input mode (PC0=1, PC1=0, PC2=0). The output driver is in high impedance

while the input section is active (see Chapter 23: GENERAL PURPOSE I/O PORTS on

page 343).

Being each GPIO pin configured in Input during Reset phase, the IO pins are released to High

Impedance condition. To avoid power consumption the user has to drive the IOs to stable

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