STR720RBQ6 datasheet(52/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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7.3 Functional Description

The EIC (Enhanced Interrupt Controller) implements an interrupt structure pointing the

processor at the first instruction location of the channel-specific Interrupt (IRQ) Service

Routine.

IVR (Interrupt Vector Register) is the EIC’s 32-bit register at address offset + 18h acting as

pointer. It is composed by two main fields: the upper half word (16 bit) is directly

programmable, while the lower half word is the mirrored entry of a register table (named SIR)

indexed by the interrupt channel. The upper part is generally meant to contain jump opcode or

base jump address depending on the application. The lower part supplies different jump

offsets as a function of the interrupt channel.

The FIQ interrupt channels have not been provided with any vectoring nand/nor priority

mechanism.

The EIC supports a fully programmable interrupt priority structure. Sixteen priority levels are

available to define the channel priority relationships. Each channel has a 4-bit field, that

defines its priority level in the range 0 - 15.

The on-chip peripheral channels and the external interrupt sources can be programmed

within these 16 priority levels, level 15 indicates the highest priority, whereas level 0 the

lowest.

If several units are located at the same priority level, an internal daisy chain, fixed for each

device and depending on which interrupt input line the device is connected to, defines the

priority relationship within that level. The higher is the input line index, the higher is the priority

in the daisy chain. The user should keep this in mind avoiding that an interrupt, with a lower

rank in the internal daisy chain, is never executed because it is at the same priority level of

another interrupt channel with higher occurrence rate.

Example:

Supposing the following hardware configuration is implemented:

Module A:

Interrupt channel 2

Module B:

Interrupt channel 6

If both the priority levels have been set to 5, and both modules generate simultaneously an

interrupt request to the EIC, the request from Module B is served first.

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