STR720RBQ6 datasheet(59/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Interrupt Vector Register (IVR)

Address Offset: 18h

Reset value: 0000 0000h

The IVR is the EIC register the processor has to read after detecting the nIRQ signal

assertion.

The IVR read operation tells the EIC logic that the interrupt service routine (ISR), related to

the pending request, has been initiated.

This means that:

•

the IRQ signal can be de-asserted

•

the CIPR and CICR can be updated

•

no interrupt requests, whose priority is lower, or equal, than the current one can be

processed

Bit 31:16 = IVR(31:16): Interrupt Vector (High portion).

its content does not depend on the interrupt to be serviced, but has to be programmed by the

user (see Note) at initialization time and it’s common to all the interrupt channels. It is Read/

Write.

Bit 15:0 = IV(15:0): Interrupt Vector (Low portion).

its content depends on the interrupt to be serviced (i.e. the one, in the enabled bunch, with the

highest priority), and it’s a copy of the SIV (Source Interrupt Vector) value of the SIR (Source

Interrupt Register) related to the channel to be serviced. It is Read only.

Note

The EIC logic does not care about the IVR content: from the controller point of view

it’s a simple concatenation of two 16-bit fields

•

IVR = IVR(31:16) & SIRn(31:16)

What has to be written both in the IVR(31:16) and in all the SIRn(31:16) is mostly

implementation dependent, but two main settings can be recognized:

•

IVR(31:0) contains a 32 bit address

IVR[31:16]

765432

IVR[15:0]

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