công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

STR720RBQ6 bảng dữ liệu(PDF) 56 Page - STMicroelectronics

tên linh kiện STR720RBQ6
Giải thích chi tiết về linh kiện  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR720RBQ6 bảng dữ liệu(HTML) 56 Page - STMicroelectronics

Back Button STR720RBQ6 Datasheet HTML 52Page - STMicroelectronics STR720RBQ6 Datasheet HTML 53Page - STMicroelectronics STR720RBQ6 Datasheet HTML 54Page - STMicroelectronics STR720RBQ6 Datasheet HTML 55Page - STMicroelectronics STR720RBQ6 Datasheet HTML 56Page - STMicroelectronics STR720RBQ6 Datasheet HTML 57Page - STMicroelectronics STR720RBQ6 Datasheet HTML 58Page - STMicroelectronics STR720RBQ6 Datasheet HTML 59Page - STMicroelectronics STR720RBQ6 Datasheet HTML 60Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 56 / 401 page
background image
STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)
56/401
7.4 Register Description
Reading from the “Reserved” field in any register will return ‘0’ as result. Attempt to write in the
same field has no effect.
Interrupt Control Register (ICR)
Address Offset: 00h
Reset value: 0000 0000h
Bit 31:2 = Reserved.
Bit 1= FIQ_EN: Global FIQ output ENable bit
This bit enables FIQ output request to the CPU.
1: Enhanced Interrupt Controller FIQ output request to CPU is enabled
0: Enhanced Interrupt Controller FIQ output request to CPU is disabled, even if the EIC logic
has detected valid and enabled fast interrupt requests at its inputs
Bit 0 = IRQ_EN: Global IRQ output ENable bit
This bit enables IRQ output request to the CPU.
1: Enhanced Interrupt Controller IRQ output request to CPU is enabled
0: Enhanced Interrupt Controller IRQ output request to CPU is disabled, even if the EIC logic
has detected valid and enabled interrupt requests at its inputs
The ICR register is an enable register at the EIC IRQ/FIQ outputs level: it has no influence on
the EIC internal logic behaviour.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
-
15
14
13
12
11
10
9
8
765432
1
0
reserved
FIQ_EN IRQ_EN
-rw
rw
1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com