STR720RBQ6 datasheet(64/401 Pages) STMICROELECTRONICS

64 / 401 page

STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

64/401

Remark:

The Interrupt Pending bits must be handled with care because the EIC State Machine, and its

internal priority hardware stack, could be forced to a not recoverable condition if unexpected

pending bit clear operations are performed.

Example:

1. suppose that one or more interrupt channels are enabled, with a priority higher than zero;

as soon as an interrupt request arises, the EIC FSM processes the new input and asserts

the nIRQ signal. If, before reading the IVR (0x18) register, for any reason, the processor

clears the pending bits, the nIRQ signal will remain asserted the same, even if no more

interrupts are pending.

The only way to reset the nIRQ line logic is to read the IVR (0x18) register.

2. suppose that one or more interrupt channels are enabled, with a priority higher than zero;

as soon as an interrupt request arises, the EIC FSM processes the new input and asserts

the nIRQ signal. If, after reading the IVR (0x18) register, for any reason, the processor

clears the pending bit related to the serviced channel, before completing the Interrupt Ser-

vice Routine, the EIC logic will detect an End Of Interrupt command, will send a pop

request to the priority stack and a new interrupt, even of lower priority, will be processed.

To close an interrupt handling section End Of Interrupt (EOI), the interrupt pending clear

operation must be performed, at the end of the related Interrupt Service Routine, on the

pending bit related to the serviced channel; on the other hand, as soon as the pending bit of

the serviced channel is cleared (even by mistake) by the software, the EOI sequence is

entered by the EIC logic.

STR720RBQ6 bảng dữ liệu(PDF) 64 Page - STMicroelectronics