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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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7.6.2

Hints about subroutines used inside ISRs

A case in which a subroutine is called by an ISR is hereafter considered.

Supposing that such a kind of procedure starts with an instruction like:

STMFD SP!, { ... , LR }

probably it will end with:

LDMFD SP!, { ... , LR }

MOV

PC, LR

If a higher priority IRQ occurs between the last two instructions, and the new ISR calls in turn

another subroutine, LR content will be lost: so, when the last IRQ ends, the previously

interrupted subroutine will not return to the correct address.

To avoid this, the previous two instructions shall be replaced with the unique instruction:

LDMFD SP!, { ... , PC }

which automatically moves stored link register directly into the program counter, making the

subroutine correctly return.

7.7 Interrupt latency

As soon as an interrupt request is generated (either from external interrupt source or from an

on-chip peripheral), the request itself must go through three different stages before the

interrupt handler routine can start. The interrupt latency can be seen as the sum of three

different contributions:

■

Latency due to the synchronisation of the input stage. This logic can be present (e.g.

synchronization stage on external interrupts input lines) or not (e.g. on-chip interrupt

request), depending on the interrupt source. Either zero or two clock cycles delay are related

to this stage.

■

Latency due to the EIC itself. Two clock cycles are related to this stage.

■

Latency due to the ARM720T Release 3 interrupt handling logic (refer to the documentation

available on www.arm.com).

Table 23. Interrupt latency (in clock cycles)

SYNCH. STAGE

EIC STAGE

min

max

FIQ

IRQ

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