SCD1283 datasheet(61/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.3.6

Parallel Auxiliary Control Register

The PACR provides some special functions for the parallel data path and interrupt-generation

circuitry.

The upper 2 bits are used to change the basic timing of the timers associated with the data pipeline.

Bit 5 can disable the stale data time.

7.3.7

Parallel Channel Reset Register

Access: R/W

8-Bit Hex Address: 3F

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

ShrtTen

ShrtStal

StaleOff

FIFOlock

ClearTO

AsyncDMA

Bit

Description

ShrtTen: This function shortens the Prescaler count cycle that generates the internal 10-

µs clock (based on a

25-MHz system clock) for the stale data counter. This bit is cleared by RESET*. If set, 10-

µs ‘ticks’ of the counter will

be generated every two CLKs; the normal period is one ‘tick’ every 250 CLKs.

ShrtStal: This function shortens the period of the stale data timer. The stale data timer includes a divide-by-ten

prescaler; setting this bit bypasses the prescaler function, causing the stale data timer to count on each 10-

µs clock

‘tick’.

If both ShrtTen and ShrtStal are set, the stale data timer counts on every other CLK.

StaleOff: When this bit is set, it masks off the Stale Status bit. The inverse of this bit is AND’ed with the stale state

condition of the parallel channel to produce the stale status and has the effect of disabling OneChar and Stale as

interrupt sources. StaleOff is provided primarily for test and development purposes, when slow movement of data

into the parallel port might cause Stale and OneChar to always appear true.

FIFOlock: This bit causes the FIFO to stop accepting data from the parallel channel state machine. This action

makes the FIFO appear full to the parallel port, thus causing it to enter the ‘busy’ state. This function is primarily

intended for use in system testing to cause a timeout on the 1284 bus.

Setting this bit in ECP Forward mode may cause a stall condition event 35 because event 36 will not occur until

FIFOlock is cleared. The ECP mode host transfer recovery handshake sequence (from event 35 stall) is supported

and the byte transit discarded as required by the specification. This bit does not provide an effective means to flow

control the host.

ClearTO: The Clear Timeout bit is a reset bit for the timeout status latch logic. When toggled by software, the timeout

status in the PFSR is cleared; it may be left set to disable the Timeout status function. Note that if this bit is left set,

the OneChar interrupt condition will never become true since there will be no FIFO timeout activity.

Reserved: This read-only bit is always ‘0’.

AsyncDMA: This bit causes the device to synchronize the DMAACK* signal to the internal clock (rising clock edge).

This capability provides an asynchronous DMA interface for systems that cannot meet the setup times required by

the synchronous DMA logic.

Refer to the Section 8.3.1 on page 78 for specific timing relationships between CLK and DMAACK* when

AsyncDMA is enabled.

Reserved: This read-only bit is always ‘0’.

Access: R/W

8-Bit Hex Address: 6C

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PChReset

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