SCD1283 datasheet(73/94 Pages) INTEL

73 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

This register allows the peripheral host processor to issue special commands to the channel control

state-machine. In response, the state-machine will perform the indicated IEEE STD 1284-defined

handshake on the parallel interface.

7.4.12

Short Pulse Register

This register performs two functions:

1. SPR sets the duration of the short pulse used by the IEEE 1284 protocols for all modes other

than Compatibility.

2. In Compatibility mode, SPR sets the duration of the ACK* pulse.

For Non-compatibility modes, SPR must be set to n

− 2, where n is the number of CLKs in a 500-

ns pulse. The peripheral host initializes SPR with the appropriate value to generate a 500-ns pulse

width based on the operating frequency of the device.

In Compatibility mode, SPR should be set to the desired length of the ACK* pulse. This is

provided to enable the device to interface to slow masters that require an ACK* pulse longer than

the maximum specified in the IEEE 1284 specification. Table 11 shows examples of the necessary

binary value for various system clock frequencies to set the 500-ns pulse width.

Bit

Description

7:5

These read-only bits are always ‘0’.

TestMux: When this bit is set, the state of the state machine is multiplexed onto the GPIO pins for debugging

purposes.

GPIO is not possible when this bit is set.

3:2

Clear Pause and Set Pause: The Set and Clear Pause commands implement an error pause in Compatibility

mode. Usually, errors are presented to the host parallel port by the peripheral during the active BUSY period

of a data transfer. SetPs remains set until ClrPs is set, at which time both will clear.

In most cases, the slave host also sets RevRq at the same time when SetPs is set to:

1) lockup Compatibility mode with BUSY high, and

2) request a reverse transfer if the master requests that an additional status be sent in the reverse direction.

EPP Interrupt Request: This command causes the state machine to generate the EPP interrupt sequence.

The EPIrq bit clears on the initiation of the Intr (PerClk) pulse on the parallel port interface.

Reverse Request: This command requests that the host parallel port initiate the defined interface reversal

handshake as defined by the IEEE Std 1284 specification. The command bit clears to indicate completion

after the command has been executed on the interface. For Reverse Nibble and Reverse Byte modes, this

occurs after negotiation is complete; in ECP mode, it occurs after the Reverse Request signal on the parallel

port interface goes low.

In ECP mode, nPeriphRequest (nFault) is driven low to request that the host-side parallel port reverse the

direction of the interface.

When this bit is set upon termination to Compatibility mode, the CD1283 can indicate that reverse data is

available (through the nDataAv signal) immediately upon recognition of a Reverse-Nibble or Reverse-Byte

negotiation. To obtain this behavior, this bit should be initialized to ‘1’, and set to ‘1’ upon termination to

Compatibility mode.

Access: R/W

8-Bit Hex Address: 26

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8-Bit Binary Value

SCD1283 bảng dữ liệu(PDF) 73 Page - Intel Corporation

SCD1283 bảng dữ liệu(HTML) 73 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

bảng dữ liệu tải về

Link URL