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SCD1283 bảng dữ liệu(PDF) 85 Page - Intel Corporation |
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SCD1283 bảng dữ liệu(HTML) 85 Page - Intel Corporation |
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85 / 94 page ![]() IEEE 1284-Compatible Parallel Interface — CD1283 Datasheet 85 Table 13. Synchronous Timing Reference Parameters Timing Number Figure Parameter MIN MAX Unit t1 26 Setup time, CS* and DS* to C1 rising edge 15 ns t2 26 Setup time, R/W* to C1 rising edge 15 ns t3 26 Setup time, address valid to C1 rising edge 20 ns t4 26 C2 rising edge to data valid 60 ns t5 26 DTACK* low from C3 rising edge1 30 ns t6 26 CS* and DS* trailing edge to data bus high-impedance 30 ns t7 26 CS* and DS* inactive between host accesses 10 ns t8 26 Hold time, R/W* after C3 rising edge 20 ns t9 26 Hold time, address valid after C3 rising edge 0 ns t10 27 Setup time, write data valid to C2 rising edge 0 ns t11 28 Setup time, DS* and DGRANT* to C1 rising edge 30 ns t12 28 Setup time, SVCACK* to DS* and DGRANT* 10 ns t13 27 Hold time, write data valid after C3 rising edge 0 ns t14 29 Propagation delay, DS* and DGRANT* to DPASS* 35 ns t15 29 30 Falling edge DMAREQ* after rising edge CLK (DMA write/read) 25 ns t16 29 30 Hold time, rising edge DMAREQ* after falling edge DMAACK* (DMA write/read) 20 ns t17 29 Setup time, data valid before rising edge C3 (DMA write) 5 ns t18 29 30 Setup time, falling edge DMAACK* to falling edge C1 (DMA write/read) 10 ns t21 26 DTACK* active pull-up time2 t22 30 Hold time, data valid after rising edge C3 (DMA write) 5 t23 30 Hold time, data valid after rising edge C1 (DMA read) 10 30 t24 30 Data valid after falling edge C1 (DMA read) 25 t25 30 Inactive time, DMAACK* (DMA read) 10 NOTES: 1. On host I/O cycles immediately following SVCACK* cycles and writes to the EOSRR, DTACK* will be delayed by 20 CLKs (1 ms @ 20 MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, use wait states or some other form of delay generation to assure that the CD1283 is not accessed until after this time period. 2. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* enters the ‘open-drain’ (high-impedance) state. |
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