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SCD1283 bảng dữ liệu(PDF) 38 Page - Intel Corporation |
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SCD1283 bảng dữ liệu(HTML) 38 Page - Intel Corporation |
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38 / 94 page ![]() CD1283 — IEEE 1284-Compatible Parallel Interface 38 Datasheet 5.5.6 Manual Mode Manual mode allows direct control of the five output control signals and the PD bus. It is not intended for data transfers, but rather for advanced diagnostics. Enter Manual mode by setting the ManMd bit (PCR[7]) when the interface is in Compatibility mode. The MMDir bit (PCR[1]) sets the direction of the PD bus: 0 = input; 1 = output. When the MMDir bit is set to ‘1’, data for the PD bus comes from the MDR. The ManOE bit controls the tristate buffer on the PD bus: 0 = floating; 1 = driving. When MMDir is ‘0’, ManOE is ignored, PD[7:0] are inputs, and the data can be read in the MDR. 5.5.7 Control Signals Output signals are controlled by the OVR. The degree of control depends on the current mode. In Manual mode, all five signals are under user control. In Compatible and EPP modes, only three signals are available, the others are set by the state machine. IVR, ZDR, ODR, and SSR monitor the four input signals. These four registers have a common format. The IVR always shows the values of the four input pins. ZDR and ODR allow the user to force interrupts on specific signal transitions. Bits set in the ZDR generate an interrupt, if the specified signal changes from ‘1’ to ‘0’. Similarly, bits set in the ODR generate an interrupt if the specified signal changes from ‘0’ to ‘1’. When both bits are set, interrupts are generated on either transition. The SSR shows the status of signal changes according to ZDR and ODR. SSR shows which signal changed. (It is necessary for the user to read the IVR to determine how the signal changed.) The signal change interrupt is enabled with the SigCh bit (PCIER[4]). Figure 8. FIFO Data Path Functional Diagram: Transmit DB[15:8] DB[7:0] (TRANSMIT) FIFO (64 BYTES) TAG (64 BITS) PFSR TAG TAG TAG BIT STATUS STATUS |
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