SCD1283 datasheet(74/94 Pages) INTEL

74 / 94 page

CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

7.4.13

Signal Status Register

The bits in this register show the results of changes specified in the ODR and ZDR. Normally, the

host will read this register in response to a signal-change interrupt generated by the CD1283. SSR

is active and valid only in Manual mode. Bits 7:4 return zeros when read. A write of any value to

SSR clears it.

7.4.14

Zeros Detect Register

When the bits 3:0 in ZDR are set, it enables the CD1283 to generate an interrupt (if the SigCh bit in

PCIER is set) when the selected signal changes from high-to-low (falling edge). Bits 7:4 are

reserved and must be written as ‘0’; these bits return ‘0’ when read. This register is enabled only

during Manual mode.

7.5

Special Register

7.5.1

Reset Command Register

Table 11. SPR Binary Values to Set 500-ns Pulse Widths

Clock

(MHz)

SPR Value

Resultant Pulse Width

(ns)

500

520

Access: R/W

8-Bit Hex Address: 2F

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A1284

nInit

HstBsy

HstClk

Access: R/W

8-Bit Hex Address: 2C

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

A1284

nInit

HstBsy

HstClk

Access: R/W

8-Bit Hex Address: 05

Default Value: 00

Bit 7Bit 6Bit 5Bit 4Bit 3

Bit 2Bit 1

Bit 0

000

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