SCD1283 datasheet(67/94 Pages) INTEL

67 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.3.17

Stale Data Timer Period Register

This register provides a user-defined period value for use as the timeout value of the stale data

timer (see SDTCR).

With a 25-MHz CLK input to the device, the resolution of this timer is 0.1 ms, its maximum value

is 25.5 ms. The 25-MHz clock is divided by 250 to produce a 10-

µs intermediate clock for this

timer. A fixed, divide-by-ten prescaler produces 0.1-ms ‘ticks’ to the stale data timer. The prescaler

is reset each time the stale data timer is reloaded to ensure accuracy for small time-out values. (A

user selection of a 0.1-ms timeout would result in a time delay of between 0.09 and 0.1 ms.)

The SDTPR is cleared by device reset.

7.4

Parallel Port Registers

7.4.1

EPP Address Register

This register is only used during EPP mode. The CD1283 deposits the value obtained during an

EPP address write command in this register. The CD1283 provides this value in response to an EPP

address read command.

7.4.2

Input Value Register

This register always shows the current state of the external handshake pins.

Access: R/W

8-Bit Hex Address: 3C

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8-Bit Stale Data Timeout Value

Access: R/W

8-Bit Hex Address: 25

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8-Bit Binary Value

Access: Read only

8-Bit Hex Address: 2E

Default Value: XX

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A1284

nInit

HstBsy

HstClk

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