SCD1283 datasheet(25/94 Pages) INTEL

25 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

FIFO has less than 2 bytes remaining (reverse direction). In the forward direction, the DMA

controller logic responds by placing data on the 16-bit data bus and driving the DMAACK* input

low. This cycle is repeated until the FIFO has less than two empty byte locations remaining or there

is no more data to send. In the reverse direction, the CD1283 responds to the active DMAACK*

signal by driving the contents of the DMABUF register onto the data bus.

Odd-byte transfers in the reverse direction are handled on an interrupt basis. When the number of

bytes in the FIFO is odd, all bytes except the last are transferred through a number of 16-bit DMA

cycles (two bytes per cycle). The odd byte remaining is held in PFHR1 and an interrupt generated

when the stale data timer expires. Status indicating that PFHR1 contains data is indicated in the

PFSR. The CPU interrupt service routine must manually remove the remaining byte from the

interface. In the forward direction, an odd remaining byte can be directly written to the PFHR1

once the last DMA cycle is complete.

One additional input signal determines the endian format (whether the least-significant byte is on

data bits 7:0 or 15:8) of the 16-bit DMA buffer. BYTESWAP selects whether the lower or upper

byte of the DMA buffer moves into the FIFO data pipeline first in the forward direction, or from the

FIFO data pipeline to the DMA buffer first in the reverse direction. If BYTESWAP is low, then the

least-significant byte (DB[7:0]) immediately moves into or out of the data pipeline. If BYTESWAP

is high, the opposite occurs (DB[15:8] move into or out of the pipeline first).

The effective duration of the DMA transfer block (burst) is determined by the threshold value in the

PFTR. Regardless of where the port is moving data when this threshold is reached (exceeded in

receive; less than in transmit), a DMA cycle begins and remains active until the FIFO has less than

2 bytes remaining (receive) or has less than two empty byte locations remaining (transmit).

The SVRR provides can determine if a DMA cycle is being requested. SVRR[7] is true if a DMA

cycle is currently being requested. This status indication is provided as a general system status.

Refer to Chapter 8.0 for detailed information on DMA cycle options and timing values.

5.2.5

Interrupts

The term interrupt is a generalized description of the method where the CD1283 gains the attention

of the CPU. Interrupt is used interchangeably with ‘service request’ as the two are the same

function. Interrupt often describes an unconditional response on the part of the CPU. Whether or

not this is the case, the source is still the same — a service request from the CD1283. The hardware

signal generated by the CD1283 (SVCREQP*) can be connected to the CPU interrupt input to start

an interrupt service routine. The service routine can then begin servicing the request from the

CD1283 by starting an acknowledge sequence.

5.2.6

DMAREQ* as Interrupt Source

Interrupts are not generated by FIFO threshold conditions; therefore, if the system design requires

data to move through interrupts, connect DMAREQ* directly to a CPU interrupt input or logically

OR it into the same CPU interrupt input as SVCREQP*. If DMAREQ* is used to generate

interrupts, the following are required:

1. A 16-bit data interface must be implemented to support 16-bit reads of the DMABUF register.

2. The DMA threshold value in the PFTR must be initialized.

3. The DMAREQ* remains active until the FIFO is nearly empty (Rx) or nearly full (Tx),

followed by the toggling of DMAen if data is moved to/from the FIFO through PIO (refer to

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