SCD1283 datasheet(35/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

5.4.5

Receiving Compressed Data

RLE compressed data sequences that consist of a tagged RLE count followed by the compressed

data character, are stored in the FIFO in compressed form. As data is moved from the FIFO into the

data pipeline, the tag bit is inspected. If the tagged data is an RLE count (HostAck signal is high)

and RLEen is true, the RLE count is loaded into the RLCR instead of PFHR1; the next data

character is loaded into PFHR1. Decompression occurs by holding the compressed character in

PFHR1 as copies of the character are shifted forward into PFHR2. As each copy of the character is

shifted, the RLCR value decrements. When the RLCR has reached zero, the hold on PFHR1 is

released and it can shift forward in the pipeline as ordinary data.

Tagged data from the FIFO is recognized to be an ECP mode address and shifts into the pipeline

where it causes an interrupt to the CPU to remove the tagged data from the pipeline. If RLEen is

‘0’, all tagged data from the FIFO is shifted into the pipeline and produces CPU interrupts.

If an immediate termination occurs between the reception of the RLE count and the corresponding

data, then the RLE count is stored in RLCR and the next data byte received in ECP mode is

uncompressed into the FIFO (based on the values in RLCR provided and if RLEen is still set). If

the next byte received in ECP mode is a new RLE count, then that value overwrites the old value in

the RLCR.

5.4.6

Stale Data (Stale, OneChar, and Timeout Status Bits)

Data transfers to the CPU can also be initiated by the stale data timer. This timer is reloaded with

the value in the SDTPR and restarts each time data is placed into the FIFO from the parallel port.

When the timer reaches zero, the status indication stale bit (PFSR[2]) is set true unless StaleOff

(PACR[5]) is true.

StaleOff keeps the stale status bit false, even though the SDTCR counter value is zero. Should the

stale status become true with at least two characters of data available, a DMA request is made to

transfer the data. If the stale status is true and there is exactly one character available, the OneChar

status bit (PFSR[1]) is set and an interrupt generated to the CPU to transfer the single residual

character.

The PFSR indicates the Stale, OneChar, and FFempty conditions. The HRSR shows that PFHR2

contains the final character. An odd number of bytes cannot be transferred by DMA. If a DMA

transfer completes with one byte of data remaining, the data is held pending arrival of additional

data or the expiration of the stale data timer.

The OneChar status is latched true when the FIFO and the DMA buffer are empty, and there is one

character in the pipeline in PFHR2. While the OneChar status is true, further pipeline operations

are inhibited. If additional data arrives in the FIFO, it remains there until the CPU:

1. services the interrupt caused by the OneChar status, and

2. reads the data character from PFHR2.

If new data has arrived since the OneChar status bit was latched, the FFempty bit will be false.

When the CPU reads the single character from PFHR2, any newly arrived data in the FIFO

immediately moves forward into the pipeline and a DMA transfer can begin if conditions warrant.

Another latched status condition associated with the stale data timer is the Timeout status bit

(PFSR[5]). Timeout is reset by the FIFOres bit (PFCR[7]) and the ClrTO bit (PACR[3]). Timeout,

OneChar, and DataErr are pipeline interrupt conditions and, if enabled, generate an interrupt. In the

receive direction, the Timeout condition is armed when Stale is ‘0’ and ClrTO and FIFOres are also

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