SCD1283 datasheet(56/94 Pages) INTEL

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CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

7.2

Virtual Registers

The CD1283 has two operational contexts: a normal context that allows host access to most

registers and any channel, and a service-acknowledge context, allowing host access to some

registers specific to the channel requesting service. This special set of registers is called ‘virtual’

because they are only available to host access and are valid during this service-acknowledge

context; at all other times, their contents will be undefined and must not be written to by host

software.

The use of Virtual registers and context switching allows the CD1283 to maintain all channel-

specific information. The host need not make any changes to chip registers to access the registers

pertinent to the parallel channel.

The service-acknowledge context is entered in one of two ways: either through activation of the

SVCACKP* input pin (hardware activated), or through host software when the contents of any one

of PIR is copied into the AER by host software during a Poll-mode Acknowledge cycle (software-

activated). See Chapter 5.0 for a discussion of the differences between these two modes.

7.2.1

End-of-Service Request Register

The EOSRR is a ‘dummy’ location and is used to signal the end of a hardware-activated service-

acknowledge procedure, invoked by the activation of SVCACKP*. The data pattern written is a

‘don’t care’ value. Writing this location causes the CD1283 to perform its internal switch out of the

service-acknowledge context. This register is used only during a hardware-activated service

acknowledge and must not be written during Poll-mode operation.

7.2.2

Parallel Interrupt Vector Register

The value in this register is placed on the data bus, DB[7:0], when SVCACKP* is activated in

response to an active SVCREQP*. See Section 7.3.5 on page 60 for more details on the LIVR.

Access: Write only

8-Bit Hex Address: 60

Default Value: XX

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

XXXXX

Access: Read only

8-Bit Hex Address: 40

Default Value: 00

Bit 7Bit 6Bit 5

Bit 4

Bit 3Bit 2Bit 1Bit 0

User-Defined – Upper 5 Bits of LIVR

IT2

IT1

IT0

Table 10. PIVR[2:0] Encoding

IT2

IT1

IT0

Description

No active interrupt.

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