SCD1283 datasheet(16/94 Pages) INTEL

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CD1283 — IEEE 1284-Compatible Parallel Interface

Datasheet

3.3

Pin Descriptions

Symbol

Pin No.

Type

Description (Sheet 1 of 3)

A[6:0]

84–90

ADDRESS BUS: Together with CS* or one of the SVCACK* inputs and DS*, this input

selects an on-chip register for a read or write operation or an acknowledgment to a

service request.

BYTESWAP

BYTESWAP: This input determines the byte order for 2-byte DMA transfers and for

writes to the DMABUF register.

If BYTESWAP is set to ‘1’, Data Bus bits 15:8 are driven with the byte transferred first

on the parallel port bus. Data Bus bits 7:0 are driven with the byte transferred second

on the parallel port bus. If BYTESWAP is set to ‘0’, the data order is reversed, bits 7:0

are driven with the first byte transferred, and bits 15:8 are driven with the second byte

transferred.

CLK

SYSTEM CLOCK: This input has a 25 MHz maximum; 16 MHz is the recommended

minimum for satisfactory device performance.

CLK/2

SYSTEM CLOCK DIVIDED BY TWO OUTPUT: This signal is equivalent to the internal

operating clock of the device.

CS*

ACTIVE-LOW CHIP SELECT: When active, the input CS* in conjunction with DS*,

initiates a I/O cycle with the CD1283. CS* must be set to ‘1’ during DMA read/write

operations.

DB[15:0]

92–99, 2–9I/O

BIDIRECTIONAL DATA BUS [15:0]: Only DMA transfers and writes to the DMA Buffer

Buffer register, only bits 7:0 are written to the addressed register. Register reads

duplicate the register contents on both the lower byte, bits 7:0, and upper byte, bits

15:8.

DS*

ACTIVE-LOW DATA STROBE: During an active I/O cycle, the input DS* strobes data

into on-chip registers on write cycles or enables data onto the data bus during read

cycles. DS* is ignored during DMA operations.

DTACK*

ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE: This output indicates: when the

device has completed the requested I/O operation, and when the cycle may finish. This

signal can be used to implement wait-state insertion for the local CPU. It is an Active

Release output, driving to logic ‘1’ then releasing to OD. DTACK* must be tied to

external VCC with a pull-up resistor. DTACK* is not activated on DMA cycles.

OUTEN

OUTPUT ENABLE: This pin must be set to ‘1’ to enable output pin functions. When

OUTEN is set to ‘0’, it forces all pins that can act as outputs to remain in a tristate

condition.

OUTEN is used as a test input and is not normally used in an end application. User

designs should tie this pin to VCC through a pull-up resistor.

RESET*

ACTIVE-LOW RESET INPUT: Initializes the device to the default condition. All internal

registers are set to their reset condition and all transfer operations are set to the default

state.

R/W*

READ/WRITE*: This pin must be set to ‘1’ for a register read operation and set to ‘0’

for a register write operation. This input is ignored for DMA operations.

DMAREQ*

ACTIVE-LOW DMA REQUEST: When the internal control bit DMAen is set, the output

DMAREQ* is asserted whenever internal FIFO conditions warrant a DMA transfer.

DMAREQ* is deasserted on the falling edge of DMAACK* when DMA transfers must

not continue past the current transfer.

DMAACK*

ACTIVE-LOW DMA ACKNOWLEDGE: This signal must never be asserted unless in

response to a DMAREQ* from the device. DMAACK* is the only bus handshake signal

recognized during a DMA transfer. (CS* must be high whenever DMAACK* is

asserted.) The direction of the DMA transfer is determined by the internal control bit

DMAdir.

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