SCD1283 datasheet(83/94 Pages) INTEL

83 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

Figure 22. Asynchronous DMA Read Cycle Timing

Figure 23. Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)

t20

t23

t24

t19

DB[15:0]

DMAACK*

CLK

‘a’

‘b’

NOTES:

1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.

2. If DMAACK* is released after point ‘a,’ but before point ‘b’ (two rising CLK edges after the falling edge of DMAACK*), DB[15:0]

is released at t20 following the rising edge of CLK. If DMAACK* is held past this edge, it controls the release of DB[15:0]; the

data bus remains active until DMAACK* becomes inactive (point ‘c’).

3. This Figure 22 is still valid, however, Figure 23 illustrates a more robust timing.

‘c’

MAY CHANGE

VALID

DMAREQ*

DB[15:0]

DMAACK*

CLK

NOTE: The falling edge of DMAACK* is synchronized internally with the rising edge of the clock when

asynchronous timing is selected by PACR[1]. The data valid time can vary by as much as one full CLK

cycle depending on when DMAACK* falling edge occurs in relation to the CLK rising edge. The minimum

DMAACK* active time must be met to ensure that the data has become valid before the rising edge of

DMAACK*. The DMAACK* can be extended to any length, which extends the data valid hold time

accordingly. If t25 is not met and DMAACK* is deasserted in less than t25 (MIN), then the data bus

tristates t27 after the third rising clock edge following the assertion of DMAACK*.

t27

t29

VALID

DMAREQ*

SEE NOTE

t28

t25

VALID

t26

DMAACK* SYNCHRONIZED

HERE

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