SCD1283 datasheet(89/94 Pages) INTEL

89 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

Figure 29. Synchronous DMA Write Cycle Timing

(Two Back-to-Back 3-Cycle DMA Writes)

Figure 30. Synchronous DMA Read Cycle Timing

(Two Back-to-Back 3-Cycle DMA Reads)

DB[15:0]

DMAACK*

CLK

NOTE: The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as

setup time (t18) is met. If DMAACK* is held active for more than 2.5 CLK cycles then the next DMA

cycle is simply delayed, but the data is still sampled on the second rising CLK edge following the

assertion of DMAACK*.

t16

VALID

DMAREQ*

t18

VALID

C1C2C3

DATA SAMPLED

HERE

t15

t25

t17

t22

t17

DATA SAMPLED

HERE

SEE NOTE

DB[15:0]

DMAACK*

CLK

NOTE: The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as

setup time (t18) is met. If DMAACK* is held active for more than 2.5 CLK cycles then the next DMA cycle

is simply delayed, but the data is still sampled on the second rising CLK edge following the assertion of

DMAACK*.

VALID

DMAREQ*

t18

VALID

C1C2C3

t15

SEE NOTE

t25

t18

t24

t16

t23

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