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LAN91C111 bảng dữ liệu(PDF) 84 Page - Microchip Technology

tên linh kiện LAN91C111
Giải thích chi tiết về linh kiện  10/100 Non-PCI Ethernet Single Chip MAC PHY
PDF  125 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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LAN91C111 bảng dữ liệu(HTML) 84 Page - Microchip Technology

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 2011-2016 Microchip Technology Inc.
DS00002276A-page 85
LAN91C111
10.5
Memory Partitioning
Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit and receive
resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the
CPU to prevent the receive process from starving the transmit memory allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the MAC for receive.
The CPU can control the number of bytes it requests for transmit but it cannot determine the number of bytes the receive
process is going to demand. Furthermore, the receive process requests will be dependent on network traffic, in particular
on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer
software flow control.
FIGURE 10-5:
DRIVE SEND AND ALLOCATE ROUTINES
AL L O C AT E
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W rite A llo ca te d Pa cke t in to
Pa cke t # Re gister
W rite Add ress Po in te r R e g ister
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Call A L LO CAT E
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Re gister



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