LAN91C111 datasheet(52/125 Pages) MICROCHIP

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LAN91C111

DS00002276A-page 52

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LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into

the EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a LINK_OK transition, will acknowl-

edge the interrupt. LE ENABLE defaults low (disabled).

CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into

the EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover, will acknowl-

edge the interrupt. CR ENABLE defaults low (disabled).

TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH

INT bit. An EPH INT interrupt caused by a transmitter error is acknowledged by setting TXENA bit in the TCR register

to 1 or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears

TXENA with TX_SUC staying low as described in the EPHSR register.

EEPROM SELECT - This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE refers to.

When high, the General Purpose Register is the only register read or written. When low, RELOAD reads Configuration,

Base and Individual Address, and STORE writes the Configuration and Base registers.

RELOAD - When set it will read the EEPROM and update relevant registers with its contents. Clears upon completing

the operation.

STORE - When set, stores the contents of all relevant registers in the serial EEPROM. Clears upon completing the oper-

ation.

8.16

Bank 2 - MMU Command Register

This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.

The three command bits determine the command issued as described below:

Note:

When an EEPROM access is in progress the STORE and RELOAD bits will be read back as high. The

remaining 14 bits of this register will be invalid. During this time attempted read/write operations, other than

polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume

accesses to the LAN91C111 after both bits are low. A worst case RELOAD operation initiated by RESET

or by software takes less than 750

s.

OFFSET

NAME

TYPE

SYMBOL

MMU COMMAND

WRITE ONLY

BUSY BIT

READABLE

MMUCR

HIGH

BYTE

LOW

BYTE

COMMAND

Reserved

BUSY

Operation Code

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