LAN91C111 datasheet(58/125 Pages) MICROCHIP

58 / 125 page

LAN91C111

DS00002276A-page 58

 2011-2016 Microchip Technology Inc.

This register can be read and written as a word or as two individual bytes.

The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being

set will cause a hardware interrupt.

MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register) change state.

LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.

These bits automatically latch upon changing state and stay latched until they are read. When they are read, the bits

that caused the interrupt to happen are updated to their current value. The MDINT bit will be cleared by writing the

acknowledge register with MDINT bit set.

Reserved - Must be 0

EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This

bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level

drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these

sources can be done via the Control Register. The possible sources are:

LINK - Link Test transition

CTR_ROL - Statistics counter roll over

TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific rea-

son will be reflected by the bits:

• SQET - SQE Error

• LOST CARR - Lost Carrier

• LATCOL - Late Collision

• 16COL - 16 collisions

Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.

• LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable)

OFFSET

NAME

TYPE

SYMBOL

INTERRUPT

ACKNOWLEDGE

WRITE ONLY

IST

MDINT

Reserved

RX_OVRN

INT

TX EMPTY

INT

TX INT

OFFSET

NAME

TYPE

SYMBOL

INTERRUPT MASK

READ/WRITE

MSK

MDINT

MASK

Reserved

EPH INT

MASK

RX_OVRN

INT

MASK

ALLOC INT

MASK

TX EMPTY

INT

MASK

TX INT

MASK

RCV INT

MASK

00000000

LAN91C111 bảng dữ liệu(PDF) 58 Page - Microchip Technology

LAN91C111 bảng dữ liệu(HTML) 58 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL