LAN91C111 datasheet(43/125 Pages) MICROCHIP

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DS00002276A-page 43

LAN91C111

TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C111 will complete

the current transmission before stopping. When stopping due to an error, this bit is automatically cleared.

8.6

Bank 0 - EPH Status Register

This register stores the status of the last transmitted frame. This register value, upon individual transmit packet comple-

tion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the

copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for

real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.

LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value

of this bit generates an interrupt.

CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by

reading the ECR register.

EXC_DEF - Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2 byte times. Cleared

at the end of every packet sent.

LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of preamble. Valid

only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset. Cleared by setting TXENA bit in TCR.

LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into

the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting

TXENA in TCR.

TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4

s of the inter frame gap. Cleared at

the end of every packet sent.

LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit

frame.

SQET - Signal Quality Error Test. This bit is set under the following conditions:

LAN91C111 is set to operate in Half Duplex mode (SWFDUP=0);

When STP_SQET=1 and SWFDUP=0, SQET bit will be set upon completion of a transmit operation and no

SQET Pulse has occurred during the IPG (Inter Frame Gap). If a pulse has occurred during the IPG, SQET bit

will not get set.

Once SQET bit is set, setting the TXENA bit in TCR register, or via hardware /software reset can clear this bit.

16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.

Cleared when TXENA is set high.

LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit

frame.

MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.

Cleared when TX_SUC is high at the end of the packet being sent.

OFFSET

NAME

TYPE

SYMBOL

EPH STATUS REGISTER

READ ONLY

EPHSR

HIGH

BYTE

Reserved

LINK_

Reserved

CTR

_ROL

EXC

_DEF

LOST

CARR

LATCOL

Reserved

-nLNK pin

LOW

BYTE

DEFR

LTX

BRD

SQET

16COL

LTX

MULT

MUL

COL

SNGL

COL

TX_SUC

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