LAN91C111 datasheet(53/125 Pages) MICROCHIP

53 / 125 page

 2011-2016 Microchip Technology Inc.

DS00002276A-page 53

LAN91C111

COMMAND SET

Operation

Code

Decimal

Value

Command

000

NOOP - NO OPERATION

001

ALLOCATE MEMORY FOR TX

010

RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant

interrupts, resets packet FIFO pointers.

011

REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has

completed processing of present receive frame. This command removes the

receive packet number from the RX FIFO and brings the next receive frame (if

any) to the RX area (output of RX FIFO).

100

REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all

memory used by the packet presently at the RX FIFO output. The MMU busy

time after issuing REMOVE and RELEASE command depends on the time when

the busy bit is cleared. The time from issuing REMOVE and RELEASE command

on the last receive packet to the time when receive FIFO is empty depends on

RX INT bit turning low. An alternate approach can be checking the read RX FIFO

101

RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified

in the PACKET NUMBER REGISTER. Should not be used for frames pending

transmission. Typically used to remove transmitted frames, after reading their

completion status. Can be used following 3) to release receive packet memory in

a more flexible way than 4).

110

ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of

transmitting a packet just loaded into RAM. The packet number to be enqueued

is taken from the PACKET NUMBER REGISTER.

111

RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO

holding the packet numbers awaiting transmission and the TX Completion FIFO.

This command provides a mechanism for canceling packet transmissions, and

reordering or bypassing the transmit queue. The RESET TX FIFOs command

should only be used when the transmitter is disabled. Unlike the RESET MMU

command, the RESET TX FIFOs does not release any memory.

Note:

• When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with

outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO

ports register before issuing the command.

• MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet num-

ber has memory allocated to it.

LAN91C111 bảng dữ liệu(PDF) 53 Page - Microchip Technology

LAN91C111 bảng dữ liệu(HTML) 53 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL