LAN91C111 datasheet(79/125 Pages) MICROCHIP

79 / 125 page

LAN91C111

DS00002276A-page 80

 2011-2016 Microchip Technology Inc.

10.4

Typical Flow of Event For Receive

SERVICE INTERRUPT – Read Interrupt Status

Option 1) Release the packet.

Option 2) Check the transmit status in the EPH

STATUS Register, write the packet number of the

current packet to the Packet Number Register, re-

enable TXENA, then go to step 4 to start the TX

sequence again.

S/W Driver

MAC Side

ENABLE RECEPTION - By setting the RXEN bit.

A packet is received with matching address. Memory

is requested from MMU. A packet number is assigned

to it. Additional memory is requested if more pages

are needed.

The internal DMA logic generates sequential

addresses and writes the receive words into memory.

The MMU does the sequential to physical address

translation. If overrun, packet is dropped and memory

is released.

When the end of packet is detected, the status word

is placed at the beginning of the receive packet in

memory. Byte count is placed at the second word. If

the CRC checks correctly the packet number is

written into the RX FIFO. The RX FIFO, being not

empty, causes RCV INT (interrupt) to be set. The

RCV_BAD bit of the Bank 1 Control Register controls

whether or not to generate interrupts when bad CRC

packets are received.

SERVICE INTERRUPT - Read the Interrupt Status

receive packet is at receive area. (Its packet number

can be read from the FIFO Ports Register). The

software driver can process the packet by accessing

the RX area, and can move it out to system memory

if desired. When processing is complete the CPU

issues the REMOVE AND RELEASE FROM TOP OF

RX command to have the MMU free up the used

memory and packet number.

S/W Driver

MAC Side

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